Am4 Pin Layout Guide

If you look at an AM4 CPU, you will notice several empty spaces (holes in the pin grid). These are reserved pins (RSVD) or "no connect" (NC) pins. AMD uses the same substrate for EPYC embedded and Ryzen desktop, so some positions simply do nothing on consumer chips.

To prevent incorrect installation, the AM4 layout is with missing pins in specific corners.

: Dedicated pins provide the x16 graphics card slot connection and chipset communication. Managing Pin Layout Issues am4 pin layout

The physical layout of the AM4 socket changed the cooler mounting holes compared to older AM3 sockets: Википедия

Always lift the retention arm fully to the vertical position before installing or removing the CPU. If you look at an AM4 CPU, you

Unlike Intel's Land Grid Array (LGA) design, AM4 utilizes a Pin Grid Array (PGA) format. This means the delicate contact pins are located directly on the underside of the processor rather than inside the motherboard socket. 1. Physical Specifications and Pin Count

Locate the golden triangle on the corner of the CPU and match it to the arrow on the motherboard socket. To prevent incorrect installation, the AM4 layout is

Examine the AM4 socket. You will see one corner (opposite the gold triangle) has a missing hole. On the CPU, there is corresponding to that position. This is not a functional pin; it is a mechanical key.

If a critical DDR4 data line or a vital CPU core power pin breaks, the system will exhibit immediate failures. Common symptoms include failing to POST, failing to detect dual-channel memory (only booting with one stick), or throwing constant blue screens (BSODs). 5. Safe Handling and Prevention Tips

: Pins for system reset (AZ_RST_L), thermal monitoring (THERMTRIP_L), and the chipset bus. Mechanical and Thermal Layout

| Pin Group | Pin Range / Zone | Description | |-----------|------------------|--------------| | (Core) | Center + inner rings | CPU core voltage (SVI2 power stages) | | VDD_SOC | Outer sections near edges | SoC/I/O voltage (memory controller, PCIe, IF) | | VDD_CRYPTO | Dedicated region | Cryptographic co-processor power | | VDD_MISC | Scattered periphery | Minor logic and PLLs | | GND | Alternating pattern around power pins | Return current & noise isolation | | CLK (CPU) | F16, G16, H15, H16 | 100 MHz differential reference clock | | CLK (FCH/ICH) | C14, D15 | 25 MHz reference for chipset | | Reset (PROCHOT) | B11 | Thermal trip & reset signalling | | SVI2 (Power management) | A12–B14 | Serial VID interface 2.0 (voltage regulation control) | | PCIe lanes x16/x8/x4 | Multiple zones | Uplink to chipset & direct GPU slots | | DRAM channels (CH A/B) | B19–C25, etc. | Memory bus (288 pins total, shared with DDR4 interface) | | USB 2.0 / 3.0 | Edge pins | Direct from SoC (not through chipset) | | SATA | Edge pins | SoC direct SATA (usually ports 0–1) | | FCH (chipset) link | Dedicated bank | PCIe 3.0 x4 to Promontory chipset |